Improved reliability of high-voltage VDMOS with reduced mask layers through optimized edge termination (Device reliability)

Category Primary study
Journal2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
Year 2016
This article has no abstract
Epistemonikos ID: f29bbe93ef4696bd03577ae0bc4ca21ee614f4c4
First added on: May 11, 2025